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Features
* * * * * * * * * * * *
Sensitive Layer Over a 0.8 m CMOS Array Image Zone: 0.4 x 14 mm = 0.02" x 0.55" Image Array: 8 x 280 = 2240 pixels Pixel Pitch: 50 m x 50 m = 500 dpi Pixel Clock: up to 2 MHz Enabling up to 1780 Frames per Second Die Size: 1.7 x 17.3 mm Operating Voltage: 3V to 5.5V Naturally Protected Against ESD: > 16 kV Air Discharge Power Consumption: 20 mW at 3.3V, 1 MHz, 25C Operating Temperature Range: 0C to +70C: C suffix Resistant to Abrasion: >1 Million Finger Sweeps Chip-On-Board (COB) package or 20-lead Ceramic DIP available for development, with Specific Protective Layer
Applications
* * * * * * * * *
PDA (Access Control, Data Protection) Cellular Phones, SmartPhone (Access e-business) Notebook, PC-add on (Access Control, e-business) PIN Code Replacement Automated Teller Machine, POS Building Access Electronic Keys (Cars, Home,...) Portable Fingerprint Imaging for Law Enforcement TV Access
Figure 1. Fingerchip Packages
Step for easy integration Sensing area Wire protection (not drawn)
Thermal Fingerprint Sensor with 0.4 mm x 14 mm (0.02" x 0.55") Sensing Area and Digital Output (On-chip ADC) FCD4B14 FingerChipTM
Chip-on-Board Package (COB)
20-pin, 0.3" Dual-Inline Ceramic Package (DIP20)
Rev. 1962C-01/02
1
Table 1. Pin Description For DIP Ceramic Package
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name GND AVE TPP VCC RST OE De0 De1 De2 De3 FPL Do3 Do2 Do1 Do0 GND ACKN PCLK TPE AVO Type GND Analog output Power Power Digital input Digital input Digital output Digital output Digital output Digital output GND Digital output Digital output Digital output Digital output GND Digital output Digital input Digital input Analog output
Die Attach is connected to pin 1 and 16, and must be grounded. FPL pin must be grounded.
GND AVE TPP VCC RST OE De0 De1 De2 De3
1 2 2 3 3 4 5 5 6 6 7 7 8 9 9 10
20 19 18 17 16 15 14 13 12 11
AVO TPE PCLK ACKN GND Do0 Do1 Do2 Do3 FPL
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Table 2. Pin Description For Chip-On-Board Package
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Name GND AVE AVO TPP TPE VCC GND RST PCLK OE ACKN De0 Do0 De1 Do1 De2 Do2 De3 Do3 FPL GND Type GND Analog output Analog output Power Digital input Power GND Digital input Digital input Digital input Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output GND GND
Die Attach is connected to pin 1, 7 and 21, and must be grounded. FPL pin must be grounded.
GND AVE AVO TPP TPE VCC GND RST PCLK OE ACKN De0 Do0 De1 Do1 De2 Do2 De3 Do3 FPL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GND
21
3
1962C-01/02
Description
FCD4B14 is part of the FingerChip Atmel monolithic fingerprint sensor family for which no optics, no prism and no light source are required. FCD4B14 is a single chip, high performance, low cost sensor based on temperature physical effects for fingerprint sensing. FCD4B14 has a linear shape, allowing for the capture of a fingerprint image by sweeping the finger across the sensing area. After capturing several images, Atmel proprietary software can reconstruct a full 8-bit fingerprint image, if needed. FCD4B14 has a small surface combined with CMOS technology, and a Chip-On-Board or ceramic dual-in-line package assembly. These facts contribute to a low-cost device. FCD4B14 delivers a programmable number of images per second, while an integrated Analog to Digital Converter delivers a digital signal adapted to interfaces such as an EPP parallel port, USB microcontroller or directly to micro-processors. Thus, no frame grabber or glue interface is necessary to send the frames. These facts make FCD4B14 an easy device to include in any system for identification or verification applications.
Table 3. Absolute Maximum Ratings(1)
Parameter Positive supply voltage Temperature stabilization power Front plane Digital input voltage Storage temperature Lead temperature (soldering, 10 seconds.) Note: Symbol VCC TPP FPL RST PCLK Tstg Tleads Comments Value GND to 6.5 GND to 6.5 GND to VCC GND to VCC -50 to +85 Unit V V V V C
Do not solder Forbidden C DIP: socket mandatory 1. Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
Table 4. Recommended Conditions Of Use
Parameter Positive supply voltage Front plane Digital input voltage Digital output voltage Digital load Analog load Operating temperature range Maximum current on TPP CL CA RA Tamb ITPP Not connected Civil: "C" grade 0 0 to +70 100 Symbol VCC FPL Must be grounded Comments Min 3V Typ 5V GND CMOS levels CMOS levels 50 Max 5.5V Unit V V V V pF pF k C mA
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Table 5. Resistance
Parameter ESD On pins. HBM (Human Body Model) CMOS I/O On die surface (Zapgun) Air discharge MECHANICAL ABRASION Number of cycles without lubricant multiply by a factor of 20 for correlation with a real finger CHEMICAL RESISTANCE Cleaning agent, acid, grease, alcohol, diluted acetone 4 hours Internal method 200 000 MIL E 12397B 2 kV 16 kV MIL-STD-883- method 3015.7 NF EN 6100-4-2 Min Value Standard Method
Table 6. Specifications
Explanation Of Test Levels I II III IV V VI D 100% production tested at +25C 100% production tested at +25C, and sample tested at specified temperatures (AC testing done on sample) Sample tested only Parameter is guaranteed by design and/or characterization testing Parameter is a typical value only 100% production tested at temperature extremes 100% probe tested on wafer at Tamb = +25C
Parameter Resolution Size Yield: number of bad pixels Equivalent resistance on TPP pin
Symbol
Test Level IV IV I I
Min
Typ 50 8x280
Max
Unit micron pixel
15 23 30 47
bad pixels
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Table 7. 5V. Power supply = +5V; Tamb = 25C; FPCLK = 1 MHz; Duty cycle = 50%; Cload 120 pF on digital outputs, analog outputs disconnected otherwise specified.
Parameter Power Requirements Positive supply voltage Digital positive supply current on VCC pin Cload = 0 Power dissipation on VCC Cload = 0 Current on VCC in NAP mode Analog Output Voltage range Digital Inputs Logic compatibility Logic "0" voltage Logic "1" voltage Logic "0" current Logic "1"current Digital Outputs Logic compatibility Logic "0" voltage(1) Logic "1" voltage Note: 1. With IOL = 1 mA and IOH = -1 mA
(1)
Symbol
Test Level
Min
Typ
Max
Unit
VCC ICC PCC ICCNAP I IV I IV I
4.5
5 7 5 35 25
5.5 10 6 50 30 10
V mA mA mW mW A
VAVx
I
0
2.9
V
CMOS VIL VIH IIL IIH I I I I 0 3.6 -10 0 1.2 VCC 0 10 V V A A
CMOS VOL VOH I I 3.5 1.5 V V
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.
Table 8. 3.3V. Power supply = +3.3V; Tamb = 25C; FPCLK = 1 MHz; Duty cycle = 50%; Cload 120 pF on digital outputs, analog outputs disconnected otherwise specified
Parameter Power Requirements Positive supply voltage Digital positive supply current on VCC pin Cload= 0 Power dissipation on VCC Cload = 0 Current on VCC in NAP mode Analog Output Voltage range Digital Inputs Logic compatibility Logic "0" voltage Logic "1" voltage Logic "0" current Logic "1"current Digital Outputs Logic compatibility Logic "0" voltage(1) Logic "1" voltage Note: 1. With IOL = 1 mA and IOH = -1 mA
(1)
Symbol
Test Level
Min
Typ
Max
Unit
VCC ICC PCC ICCNAP I IV I IV I
3.0
3.3 6 5 20 17
3.6 10 6 33 20 10
V mA mA mW mW A
VAVx
I
0
2.9
V
CMOS VIL VIH IIL IIH I I I I 0 2.3 -10 0 0.8 VCC 0 10 V V A A
CMOS VOL VOH I I 2.4 0.6 V V
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.
Table 9. Switching Performances. Tamb = 25C; FPCLK = 1 MHz; Duty cycle = 50%; Cload 120 pF on digital and analog outputs otherwise specified
Parameter Clock frequency Clock pulse width (high) Clock pulse width (low) Clock setup time (high)/reset falling edge No data change Symbol fPCLK tHCLK tLCLK tSetup tNOOE Test level I I I I IV 100 Min 0.5 250 250 0 Typ 1 Max 2 Unit MHz ns ns ns ns
Table 10. 5.0V. All power supplies = +5 V
Parameter Output delay from PCLK to ACKN rising edge Output delay from PCLK to ACKN falling edge Output delay from PCLK to Data output Dxi Output delay from PCLK to Analog output Avx Output delay from OE to data high-Z Output delay from OE to data output Symbol tPLHACKN tPHLACKN tPDATA tPAVIDEO tDATAZ tZDATA Test level I I I I IV IV 25 29 Min Typ Max 85 80 70 170 Unit ns ns ns ns ns ns
Table 11. 3.3V. All power supplies = +3.3 V
Parameter Output delay from PCLK to ACKN rising edge Output delay from PCLK to ACKN falling edge Output delay from PCLK to Data output Dxi Output delay from PCLK to Analog output AVx Output delay from OE to data high-Z Output delay from OE to data output Symbol tPLHACKN tPHLACKN tPDATA tPAVIDEO tDATAZ tZDATA Test level I I I I IV IV 34 47 Min Typ Max 110 95 85 190 Unit ns ns ns ns ns ns
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Figure 2. Reset
Reset RST
tHRST
Clock PCLK tSETUP
Figure 3. Read One Byte/Two Pixels
FPCLK
tHCLK
Clock PCLK
tLCLK
Acknowledge ACKN
tPLHACK
tPHLACKN
Data output Do0-3, De0 -3
Data # N-1
Data # N
tPDATA
Data # N+1
Video analog output AVO, AVE
Data #N
Data #N+1
Data #N+2
tPAVIDEO
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Figure 4. Output Enable
Output Enable OE
Data output Do0-3, De0 -3
Hi-Z
tZDATA Data output
tDATAZ
Hi-Z
Figure 5. No data change
PCLK
tNOOE
OE
Note:
OE must not change during TNOOE after the PCLK falls. This is to ensure that the output drivers of the data is not driving current, to reduce the noise level on the power supply.
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Figure 6. FCD4B14 Block Diagram
PCLK RST clock reset column selection 1 dummy column 1 8 lines of 280 columns of pixels 8 2240 8 odd chip temperature stabilization chip temperature sensor 4-bit ADC 4 amp line sel ACKN
even
4-bit ADC
4 8 latches
De0-3
Do0-3
analog output AVE AVO
output enable
TPP
TPE
OE
Functional Description
The circuit is divided into two main sections: sensor and data conversion. One particular column among 280+1 is selected in the sensor array (1), then each pixel of the selected column sends its electrical information to amplifiers (2) (one per line), then two lines at a time are selected (odd and even) so that two particular pixels send their information to the input of two 4-bit Analog-to-Digital Converters (3), so 2 pixels can be read for each clock pulse (4).
Figure 7. Functional Description
1 column selection 2 line sel 3 4
even
4-bit ADC
4 8 latches
De0-3
8 lines of 280 columns of pixels 8 1 dummy column
amp 4-bit ADC
Do0-3 4
odd chip temperature sensor
Sensor
Each pixel is a sensor in itself. The sensor detects a temperature differential between the beginning of acquisition and the reading of information: this is the integration time. The integration time begins with a reset of the pixel to a predefined initial state. Note that the integration time reset has nothing to do with the reset of the digital section. Then, at a rate depending on the sensitivity of the pyroelectric layer, on the temperature variation between the reset and the end of the integration time, and on the duration of the integration time, electrical charges are generated at the pixel level.
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Analog-to-Digital Converter/ Reconstructing an 8-bit Fingerprint Image
An Analog-to-Digital Converter (ADC) is used to convert the analog signal coming from the pixel into digital data that can be used by a processor. As the data rate for parallel port and USB is in the range of 1 MB per second and at least a rate of 500 frames per second is needed to reconstruct the image with a fair sweeping speed for the finger, two 4-bit ADCs have been used to output 2 pixels at a time on 1 byte. A reset is not necessary between each frame acquisition! Start sequence must consist of: 1. Set the RST pin to high 2. Set the RST pin to low 3. Send 4 clock pulses (due to pipe-line) 4. Send clock pulses to skip the first frame Note that the first frame never contains relevant information because the integration time is not correct.
Start Sequence
Figure 8. Start Sequence
Reset RST 4+1124 clock pulses to skip the first frame
Clock PCLK 1 2 3 4 1 1124 1
Reading the Frames
A frame consists of 280 true columns + 1 dummy column of 8 pixels. As two pixels are output at a time, a system must send 281x4 = 1124 clock pulses to read one frame. Reset must be low when reading the frames.
Read One Byte/Output Enable
Clock is taken into account on the falling edge and data are output on the rising edge. For each clock pulse, after the start sequence, a new byte is output on the Do0-3, De03 pins. This byte contains 2 pixels: 4-bit on Do0-3 (odd pixels), 4-bit on De0-3 (even pixels). To output the data, the output enable (OE) pin must be low. When OE is high, the Do03 and De0-3 pins are in high impedance state. This enables an easy connection to a microprocessor bus without additional circuitry-it will enable data output by using a chip select signal. Note that the FCD4B14 is always sending data: there is no data exchange to perform using read/write mode.
Power Supply Noise
IMPORTANT: When a falling edge is applied on OE (i.e when the Output Enable becomes active), then some current is drained from the power supply to drive the 8 outputs, producing some noise. It is important to avoid such noise just after the falling edge of the clock PCLK, when the pixels information is evaluated: the timing diagram figure 5 and time TNOOE defines the interval time where the power supply must be as quiet as possible. An analog signal is also available on pins AVE and AVO. Note that video output is available one clock pulse before the corresponding digital output (one clock pipe-line delay for the analog to digital conversion).
Video Output
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Pixel Order
After a reset, pixel number one is located on the upper left corner, looking at the chip with bond pads to the right. For each column of 8 pixels, pixels 1-3-5-7 are output on odd data Do0-3 pins, pixels 2-4-6-8 are output on even data De0-3 pins. Most significant bit is bit #3, least significant is bit #0.
Figure 9. Pixel Order
Pixel #1 (1,1) Pixel #2233 (280,1) B ond pads
Pixel #8 (1,8)
Pixel #2240 (280,8)
Synchronization: The Dummy Column
A dummy column has been added to the sensor to act as a specific pattern to detect the first pixel. So, 280 true columns + 1 dummy column are read for each frame. The 4 bytes of the dummy column contain a fixed pattern on the two first bytes, and temperature information on the last two bytes.
Dummy Byte Dummy Byte 1 DB1: Dummy Byte 2 DB2: Dummy Byte 3 DB3: Dummy Byte 4 DB4: Note: x represents 0 or 1 Odd 111X 111X rrrr tttt Even 0000 0000 nnnn pppp
The sequence 111X0000 111X0000 appears on every frame (exactly every 1124 clock pulses), so it is an easy pattern to recognize for synchronization purposes.
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Thermometer
The dummy bytes DB3 and DB4 contains some internal and temperature information. The even nibble nnnn in DB3 can be used to measure an increase (or decrease) of the chip temperature, using the difference between two measures of the same physical device. The following table gives values in Kelvin.
nnnn Decimal 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nnnn Binary 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
Temperature differential with code 8 in Kelvin
11.2 8.4 7 5.6 4.2 2.8 1.4 0 -1.4 -2.8 -4.2 -5.6 -7 -8.4 -11.2 < -16.8
For code 0 and 15, the absolute value is a minimum (saturation). When the image contrast becomes low because of a low temperature difference between the finger and the sensor, it is recommended to use the temperature stabilization circuitry to increase the temperature of two codes (i.e. from 8 to 10), to get at least an increase >1.4 Kelvin of the sensor. This enables to recover enough contrast to get a proper fingeprint for recognition purpose.
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Integration Time and Clock Jitter
The FCD4B14 is not very sensitive to clock jitter (clock variation). The most important requirement is a regular integration time that ensures the frame reading rate is also as regular as possible, in order to get consistent fingerprint slices. If the integration time is not regular, contrast will vary from one frame to another. Note that it is possible to introduce some waiting time between each set of 1124 clock pulses, but the overall time of one frame read must be regular. This waiting time is generally the time needed by the processor to perform some calculation over the frame (to detect the finger, for instance). Figure 10. Read One Frame
Reset RST is low Column 1 Column 2 Column 280 Dummy Column 281
1 Clock PCLK Pixels 1 & 2
2
3
4
5
6
1119
1120
1121
1122
1123
1124
3&4
5&6
7&8
1&2
3&4
7&8
DB1
DB2
DB3
DB4
Figure 11. Regular Integration Time
REGULAR INTEGRATION TIME
Frame n
Frame n+1
Frame n+2
Frame n+3
Clock PCLK 1124 pulses 1124 pulses 1124 pulses 1124 pulses
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Power Management Nap Mode
Several strategies are possible to reduce power consumption when not in use. The simplest and most efficient is to cut the power supply, using external means. A nap mode is also implemented in the FCD4B14. To activate this nap mode, user must: 1. Set the reset RST pin to high. Doing this, all analog sections of the device are internally powered down. 2. Set the clock PCLK pin to high (or low), thus stopping the entire digital section. 3. Set the TPE pin to low or disconnect TPP to stop the temperature stabilization feature. 4. Set Output Enable OE pin to high, so that output are forced in HiZ. Figure 12. Nap Mode
Nap mode Reset RST Clock PCLK Nap
In Nap Mode, all internal transistors are in shut mode. Only leakage current is drained in power supply, generally less than the tested value.
Static Current Consumption
When the clock is stopped (set to 1) and the reset is low (set to 0), the analog sections of the device drain some current and the digital section does not consume current if the outputs are connected to a standard CMOS input (= no current is drained in the I/O). In this case the typical current value is 5 mA. This current does not depend on the voltage (i.e. it is almost the same from 3V to 5.5V). When the clock is running, the digital sections are consuming current, and particularly the outputs if they are heavily loaded. In any case, it should be less than the testing machine (120 pF load on each I/O), 50 pF maximum is recommended. Connected to a USB interface chip (see application note 26 related to the FCDEMO4 kit) at 5V, and running at about 1 MHz, the FCD4B14 consumes less than 7 mA on VCC pin.
Dynamic Current Consumption
Temperature Stabilization Power Consumption (TPP pin)
When the TPE pin is set to 1, current is drained via the TPP pin. The current is limited by the internal equivalent resistance given in table 4 and a possible external resistor. Most of the time, TPE is set to 0 and no current is drained in TPP. When the image contrast becomes low because of a low temperature differential (less than one Kelvin), then it is recommended to set TPE to 1 during a short time so that the dissipated power in the chip elevates the temperature, enabling to recover contrast. The necessary time to increase the chip temperature of one Kelvin depends on the dissipated power, the thermal capacity of the silicon sensor and the thermal resistance between the sensor and the surroundings. As a rule of thumb, dissipating 300 mW in the chip elevates the temperature of 1 Kelvin in one second. With the 30 typical value, 300 mW is 3V applied on TPP.
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Packaging: Mechanical Data
Figure 13. COB: Top View (all dimensions in mm)
0.2 A 0.89 0.3 14 2.32 0.5 0.35 5.90 max 2.95 0.50 9.45 0.5* A + 0.07 1.66 - 0.01 at 0.4 height from B ref. 0.83 0.50 0.2 min 26.6 0.25* *: including burrs Dam and Fill B 1.5 max 0.790 max 0.2 max 5.20 max +0.07 17.51 -0.01 at 0.4 height from B ref. 5.45 0.30
Figure 14. COB: Bottom View (all dimensions in mm)
1.15 0.15
1 0.075 0.5 0.075
3.5 0.075
2.15 0.15 6.30 0.1 +0.08 (x3) R0.75 -0.12 +0.33 -0.25 1.5 +0.15 (x3) -0.23
1.5 0.075
1 0.15
2 0.075 2 0.15
0.75
23.85 0.1
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Figure 15. DIL Package (all dimensions in mm)
1.1 0.1
0.25 max
0.08 60
0.81 0.05 0.46 0.05 2.54 0.13 22.86 0.13 0.25 0.05 3.15 0.32 25.4 0.25 (2.45) 9.36 0.15 6.34 0.15 0.1 min NO.20 NO.11 7.87 0.25
1962C-01/02
4.75 0.1 NO.10 7.5 0.25
6.5 max
(7.62)
(0.90)
0.75 max
0.08
(0.20)
NO.1
5.4 max
18
FCD4B14
FCD4B14
Ordering Information
Package Device
FC Atmel prefix FingerChip family Device type Package C: DIP Ceramic 20 pins CB: Chip On Board (COB) Quality level -- : s tandard D4B14 C C --
Temperature range Com: 0 to +70C
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademarks of Atmel. Other terms and product names may be the trademarks of others.
1962C-01/02/xM

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